The present invention relates in general to integrated circuits (ICs), and in particular to apparatus and method for reducing noise by programmably grounding unused output terminals.
Ground bounce refers to a phenomenon in integrated circuits that is a common source of undesirable noise. Input/output (I/O) circuits typically include relatively large pull-down and pull-up transistors to enable the IC to drive heavy external loads. The pull-down transistor that connects the output node to ground, can therefore sink large amounts of current. These output transistors connect to an external pin that is usually loaded with a sizable amount of parasitic inductance. When the pull-down transistor is switched on, this parasitic inductance fights the instantaneous discharge of the output node, and causes momentary ringing on the internal ground node. This ground bounce noise is exaggerated when, on the same device, there are a number of I/Os that switch at the same time. An example of the type of IC that may have large numbers of I/Os switching simultaneously is the programmable logic device. If the amplitude of the ground bounce in the device exceeds the noise margin of another device it is driving, it may trigger momentary switching of input transistors in the other device when the intended signal from the ground bounce device is a logic low level. A ground bounce in the negative direction may cause false switching of input transistors in the ground bounce device itself, if the level of the input signal is not low enough.
Circuit designers have used various different techniques to reduce ground bounce. While techniques such as connecting decoupling capacitors very close to the ground and other power pins has helped reduce ground bounce, ground bounce remains a problem especially in high speed devices with a large number of I/O pins. There is, therefore, always room for improving the noise immunity of integrated circuits against ground bounce.
According to the present invention, in integrated circuits that may have a number of output pins, some of which may be unused at any given time, instead of leaving an unused output pin in a tri-state mode, noise immunity is enhanced by coupling the unused outputs to a power bus such as ground. The additional lead and board capacitance associated with the unused output pad adds extra ballast capacitance to ground when the node is grounded, helping to reduce ground bounce when other outputs switch. In one embodiment, the control circuitry for grounding the unused output pins is made user programmable to make more efficient use of the internal circuitry. In a preferred embodiment, the programmable grounding of the unused output pin is achieved without compromising the speed of the data path when the output is being driven. In a specific embodiment intended for programmable logic devices having programmable logic cells, or macrocells, resources from an output macrocell are used to programmably ground an unused output pin, without sacrificing the utility of the output macrocell as a buried macrocell.
Accordingly, in one embodiment, the present invention provides, in an integrated circuit, an output circuit for driving an output node, including a test circuit path coupling a signal from internal output testing circuitry to the output node, and a speed critical circuit path coupling a signal from internal logic circuitry to the output node; wherein, when the output node is unused, the output circuit couples the output node to an internal power bus via the test circuit path.
In another embodiment, the present invention provides an integrated circuit including internal circuitry configured to perform logic functions, an output driver circuit having a first input coupled to an output enable signal and a second input coupled to an output data signal, and an output connected to an output pad; and programmable ground circuitry having a speed critical signal path coupled between the internal circuitry and the output driver circuit, and a test signal path coupled between a programmable ground signal and the output driver circuit, wherein, in a first mode of operation, the output driver circuit responds to a signal from the speed critical signal path, and in a second mode of operation the output driver circuit drives the output pad to ground in response to the programmable ground signal from the test signal path.
In yet another embodiment, the present invention provides a programmable logic device including a plurality of macrocells interconnected by an array of interconnect lines, boundary scan testing circuitry, and a plurality of output circuits driving a respective plurality of output nodes, wherein each one of the plurality of output circuits includes a programmable element for grounding an associated output node via the boundary scan testing circuitry, when the associated output node is unused.
The following detailed description and the accompanying drawings provide a better understanding of the nature and advantages of the programmable rounding technique of the present invention.